Semiconductor device and method of producing the same

ABSTRACT

A semiconductor device has a MOSFET formed on a single crystalline silicon layer in an SOI structure in which the silicon layer is laminated along with an insulator on a handle wafer. To prevent the body floating effect, a recombination center region is formed connecting to the lower surfaces of source and drain regions of the MOSFET. Consequently, the holes generated within the single crystalline silicon layer just beneath a channel of the MOSFET are injected into the recombination center region by way of the single crystalline silicon layer beneath the source diffusion region and eliminated so that the body floating effect is prevented.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method forproducing the same, more specifically this invention relates to asemiconductor device to effectively prevent the body floating effect andvarious related problems in MOS field effect transistors formed on a SOI(silicon-on-insulator) substrate, and a method for easily producing thesemiconductor device.

2. Description of Related Art

A semiconductor device having various elements such as transistorsformed on a single crystalline silicon layer formed on an insulator isknown as a structure called SOI (Silicon On Insulator). The structureshown in FIG. 2 for example is disclosed on page 755 of the ExtendedAbstracts (the Spring Meeting, 1995) The Japan Society of AppliedPhysics and Related Societies. The MOS field effect transistor(hereafter simply referred to as MOS) is formed on a single crystallinesilicon (Si) layer 3 separated from a handle wafer 1 by a thickinsulator 2. The reference numeral 4 in FIG. 2 indicates a deviceisolation layer, the numeral 5 indicates a gate insulator, the numeral 6is a gate electrode, the numeral 7 is a gate electrode protectioninsulator, the numeral 8 is a gate side-wall insulator, the numerals 9and 10 are n-type highly concentrated impurity diffusion regions withrespective drain and source regions.

The special feature of SOI-MOS of the conventional art as shown in FIG.2, is that a thick device insulation layer 2, is present directlybeneath the single-crystalline silicon (Si) layer 3 so that theparasitic wiring capacitance and the drain junction capacitance arereduced to approximately one-tenth of the capacitance of an ordinary MOSformed on an Si substrate. Another feature is that the MOS is alsoisolated by insulation from the handle wafer 1 so that misoperation dueto alpha ray beam irradiation and latch-up phenomenon are essentiallyeliminated.

However, in an SOI-MOS device of this type, the single crystallinesilicon (Si) layer 3 is completely isolated from the handle wafer 1 sothat minority carriers (holes) generated for example, by the strongelectrical field of the drain tend to transiently accumulate within thesingle crystalline silicon (Si) layer 3 and cause a shifting thresholdvoltage or so-called body floating effect. This body floating effect canbe viewed as the parasitic bipolar effect that causes majority carriersto flow in as a result of a rise in electrical potential due toaccumulation of minority carriers within the single crystalline silicon(Si) layer 3. In n-channel SOI-MOS devices, (hereafter abbreviated ton-SOI-MOS) the threshold voltage fluctuates in the negative directiondue to the accumulated holes and an abnormal bump can be observed in thedevice current/voltage characteristics (kink characteristic). Thiscondition causes problems such as a large leakage current when thedevice is in the off state and a lowering the source and drain breakdownvoltage which can be a fatal defect in differential amplifiers andanalog circuits which must detect tiny differences in the electricalcurrent.

In the SOI-MOS device shown in FIG. 2, in order to prevent the abovementioned body floating effect, germanium (Ge) is ion-implanted into asource highly-concentrated impurity diffusion region 9 and a SiGe alloy14 with a Ge content of approximately 10 percent is formed. FIG. 3 showsthe energy band diagram along the channel when a voltage is applied tothe drain of the SOI-MOS device in FIG. 2. In FIG. 3, E_(Fn) is thepseudo-fermi level and E_(i) is the intrinsic fermi level. The bandgapnarrows by approximately 0.1 eV by forming the SiGe alloy 14, thevalence band E_(v) for the source is formed as shown by the broken line,and the difference in hole diffusion potential is reduced. As a result,the holes generated near the drain and accumulating within the singlecrystalline silicon (Si) layer 3 tend to diffuse within the source andbe eliminated. The conduction band E_(c) is unaffected by the SiGe alloy14 and there are no adverse effects on the behavior of electrons whichare majority carriers.

However, due to control of the valence band at the source junction thestructure shown in FIG. 2 is inadequate for eliminating the bodyfloating effect in p-channel SOI-MOS devices (hereafter abbreviated topSOI-MOS), and when germanium (Ge) is introduced into the source regionof the pSOI-MOS device, the difference in diffusion potential drops andthe breakdown voltage deteriorates. Further, in nSOI-MOS devices sincethe body floating effect cannot be adequately eliminated, and anexcessive amount of germanium (Ge) of more than 10 percent is injectedinto the source region, the problem of crystalline defects occurs due tothe difference in lattice constants of the Si (silicon) and Ge(germanium). The only way to eliminate the crystalline defects is toreduce the Ge (germanium) content however, the improved drop indiffusion potential does not amount to more than approximately 0.1 eVwhich is inadequate to eliminate the body floating effect.

The SOI-MOS device of FIG. 4 is disclosed on page 627 of the ExtendedAbstracts of the 1995 International Electron Devices Meeting and theSOI-MOS device of FIG. 5 is disclosed on page 337 of the ExtendedAbstracts of the 1992 International Electron Devices Meeting.

In the SOI-MOS device of FIG. 4, after forming the source and draindiffusion regions 9 and 10, argon (Ar) is ion-implanted and arecombination center region 15 formed within the source and drain, andthe holes that accumulated inside the single-crystalline silicon (Si)layer 3 are eliminated. However, unless the position of therecombination center region 15 versus the drain junction is optimal,then the leakage current tends to increase so that also eliminating theholes within the single-crystalline silicon (Si) layer 3 is extremelydifficult.

In the SOI-MOS device of FIG. 5 however, a portion of the junction ofthe bottom of the source 9 is destroyed by a spike 16 resulting fromabnormal diffusion of a metal electrode and the holes within thesingle-crystalline silicon (Si) layer 3 are eliminated by this spike 16.In this structure, in order to maintain a flow path for the positiveholes, from the single-crystalline silicon (Si) layer 3, a portion belowthe bottom of the source 9 is used as the P-type highly concentratedimpurity region, and a portion below the drain 10 is used as an N-typehighly concentrated impurity region to prevent the spike 16 from causinga deterioration in the transistor characteristics. As a result, thesource 9 and the drain 10 are not symmetrical and the device is notusable in general purpose.

SUMMARY OF THE INVENTION

Accordingly it is an object of the present invention to resolve theabove mentioned problems with the SOI-MOS device of the conventional artin FIG. 2, by providing an SOI-MOS device having a new structure and aproduction method for this device, applicable even to p-SOI-MOS devicesas well as complementary SOI-MOS devices and further capable ofpreventing crystalline defects in the active region and the bodyfloating effect.

It is a further object of the present invention to resolve the abovementioned problems with the SOI-MOS device of the conventional art inFIG. 4, by providing an SOI-MOS device having a new structure and aproduction method for this device, to stop the occurrence of defects inthe active regions of the source and drain and also adequately preventthe body floating effect.

A yet further object of the present invention is to resolve the abovementioned problems with the SOI-MOS device of the conventional art inFIG. 5, by providing an SOI-MOS device having a new structure and aproduction method for this device, that is widely applicable tosemiconductor integrated circuits having a symmetrical structure ofsource and drain, and also prevents the body floating effect.

A still further object of the present invention is to provide an SOI-MOSdevice not utilizing new production technology, that can activelyprevent the body floating effect and can easily be manufactured at a lowcost with conventional production technology.

In order to achieve the above mentioned object of the invention, thesemiconductor device has an MOS field effect transistor formed on thesingle crystalline silicon layer of the above mentioned SOI structurelaminated along with an insulator on the handle wafer. The surface ofthe source region and the drain region of this MOS field effecttransistor, are respectively connected to the source electrode and drainelectrode by way of a contact hole (contact area) formed on a secondinsulator formed on the above mentioned single crystalline semiconductorlayer. A recombination center region is formed connecting to the lowersurface of the source region and drain region in the lower part of thiscontact hole of the single crystalline semiconductor layer.

Restated, as shown in FIG. 1, in the single crystalline Si layer 3 arecombination center region 20 is formed at the lower part of thecontact area (contact hole) 19 electrically connected to a sourcediffusion region 9 and a drain diffusion region 10, and source electrode12 and a drain electrode 13. Consequently, the holes generated withinthe single crystalline Si layer 3 just beneath the channel are injectedinto the recombination center region 20 by way of the single crystallineSi layer 3 beneath the source diffusion region 9 and eliminated so thatthe body floating effect is prevented.

This recombination center region 20 formed just beneath the draindiffusion region 10 might become a source of current leakage when drainvoltage is applied, however the single crystalline Si layer 3 justbeneath the drain diffusion region 10 is completely depleted by theapplication of a drain voltage so the leakage current flow path to thesource diffusion region 9 is cut off and there is no possibility ofcurrent leakage flowing. Even if the positions of the source 9 and thedrain 10 are directly interchanged, the flow path of leakage currentfrom the drain is cut off in exactly the same way and the positivecarriers just beneath the channel are injected into the recombinationcenter region on the source diffusion region side and eliminated so asymmetrical (balanced) structure is obtained.

The operating principle of this invention resembles the operatingprinciple of the junction field effect transistor (JFET). In a JFET, avoltage is applied to narrow the current path in the semiconductorregion between the two matching junctions or in other words the amountof electrical current is regulated. In contrast in this inventionhowever, though the single crystalline Si layer 3 is cut off by theinsulation layer 2, the current path, namely the amount of electricalcurrent, is regulated by applying a voltage to one junction.

The characteristics of the JFET embedded in the SOI-MOS, or in otherwords the elimination of holes on the source side (forward-directionhole current) and reverse-direction leakage current on the drain side,are determined by the thickness Δt_(sol) of single crystalline Si layer3 for the matching JFET channel and also by junction length (channellength) w from the recombination center region 20 to the singlecrystalline Si layer 3 just below the gate, and the impurityconcentration Na versus that junction length w.

A computer simulation to find the forward-direction hole current or inother words, the electrical current to eliminate the body floatingeffect is shown in FIG. 6A. The leakage current characteristics for thedrain region are shown in FIG. 6B. As FIGS. 6A and 6B clearly show, eventhough the junction length w from the recombination center region 20 tothe single crystalline Si layer 3 just below the gate is an extremelysmall 50 nm, if the impurity concentration Na for the single crystallineSi layer 3 contacting the bottom of the junction is approximately10¹⁷/cm³, then there is no possibility of leakage current occurring inthe drain, a sufficient hole current can be maintained at the sourceside and the body floating effect can be eliminated.

In order to achieve the results of the above simulation, the thicknessΔt_(sol) of single crystalline Si layer 30 for the matching JFET channelis extremely critical which in turn requires strict control of thesource and drain junction depth. The ion implantation method is normallyutilized in forming these junctions. However, the problem of channelingphenomenon occurs if the crystal displacement axis and the ionimplantation angle match each other when the junctions are formed withion implantation. In this phenomenon, impurity concentrations below10¹⁷/cm³ in a region during ion implantation deviate widely from theGauss distribution and distribute even deeper. When this channelingphenomenon occurs during forming of the source and drain diffusionregions 9 and 10, the single crystalline Si layer 3 with a thicknessΔt_(sol) contacting the bottom of the junction, becomes an entirelyn-type layer, making problems likely to occur in forming the JFETchannel. Accordingly, when using ion-implantation to form source anddrain diffusion regions, the ion-implantation angle should preferably beperformed at the ±20 degrees tilted from the perpendicular to thesubstrate surface.

To achieve strict control of the source and drain junction depth,separate ion-implantation may be performed for forming drain diffusionregion and counter-conductive atoms as well as to compensate for regionsformed deeper than needed due to channeling phenomenon.

The above description, utilized N-type MOS devices for making theexplanation simple however needless to say, a P-type MOS devices may beused in the same way with only the conduction conductive type of theimpurities being reversed.

The insulator layer and the single crystalline Si layer laminated on thehandle wafer, the MOS field effect transistor formed on a singlecrystalline semiconductor layer, a second insulator layer formed on thesingle crystalline semiconductor layer, and the source and drain regionof this MOS field effect transistor, and a specified portion of thesingle crystalline semiconductor layer below this source and drainregion are formed with a (through) hole. The recombination center regionmay be formed from the source region, drain region as well as the singlecrystalline semiconductor layer below these regions by filling this holewith a metal film. In such a case, the recombination center regiondimensions are specified by means of the metal semiconductor junction.The upper surface of the recombination center region must make contactwith the lower surface of the source and drain diffusion regions. Thelower surface of the recombination center region however, may contactthe upper surface of the insulator layer or may be separated from thisinsulator layer. By keeping the insulator layer separate, the metal/Sisurface area can be widened and a large contact area (surface area ofrecombination center region) can be secured even if the hole area isreduced.

This recombination center-region may use a region conducting in theopposite direction of the source region and drain region or therecombination center region may also utilize a non-single-crystallinesilicon region such as Polycrystalline silicon.

The drain and source regions respectively have structures with regionsthat extend at the edge of the channel of the MOS field effecttransistor yet are shallower than the source and drain and also in thesame conductive type as the source and drain regions. These regionssuppress the widening of the depletion layer and improve the breakdownvoltage. In such cases, the concentration of impurities in a shallowregion in the same conductive type as source and drain may be set lowerthan in the source and drain regions.

A semiconductor device may comprise a plurality of MOS field effecttransistors mutually connected in serial or may comprise these fieldeffect transistors connected in series with capacitor devices. In suchcases, the recombination center region is formed at the opposite node ofthese capacitor devices, and is formed at the lower surface of thesource region or drain region. Also in this case, the single-crystallinesemiconductor layer below the drain diffusion region is structured toreach the depletion region at the boundary of the insulator layer, whilea drain voltage is being applied. Attaining the depletion region in thisway, cuts off the current leakage flow path to the source diffusionregion 9 so there is no possibility of current leakage flow occurring.

In the method for manufacturing the semiconductor device of thisinvention, after forming the SOI substrate by laminate-forming theinsulator layer and the single-crystalline semiconductor layer insequence on the handle wafer, the method of the known art is thenutilized to form the MOS field effect transistor on the singlecrystalline semiconductor layer, and a second insulator layer is furtherformed over the entire surface. A contact hole is formed in the secondinsulator layer and a portion of the MOS field effect transistor sourceand drain regions exposed. Ion implantation is performed by utilizingthis contact hole and the recombination center region is formed incontact with the lower surface of the source region and drain regionwithin the single crystalline semiconductor layer.

In other words, this contact hole is a connecting hole for electricallyconnecting the source and drain diffusion regions to the respectivesource electrode and drain electrodes. Ion implantation through thiscontact hole is performed to form the recombination-center region tocontact the source and drain diffusion regions within thesingle-crystalline semiconductor layer beneath this contact hole.

The element used in the ion-implantation may be a fundamental elementselected from a group consisting of group IV fundamental elements,halogen fundamental elements and rare earth metal fundamental elements.This ion-implantation forms a non-single-crystalline region in contactwith the lower surface of the source and drain regions inside thesingle-crystalline semiconductor layer as described above. A section ofthe single-crystalline semiconductor layer selected as the region tobecome amorphous during application of the accelerated voltage in theion-implantation application becomes Polycrystalline due to heattreatment performed in subsequent processes but will not return to thesingle crystalline state.

After forming the SOI substrate, MOS field effect transistor, secondinsulator layer, and the source region and drain region of the MOS fieldeffect transistor as related for the manufacturing method, a (through)contact hole is formed in the source region and drain region as well asin a specified portion of the single-crystalline semiconductor layerbelow these source and drain regions. By filling this contact hole witha metallic layer, a recombination center region is formed inside thesingle crystalline semiconductor layer and in contact with the lowersurface of the source and drain regions. In such cases, therecombination center region is separated from the single crystalline(Si) layer by a metal-semiconductor junction.

Many types of semiconductor devices can be configured for example suchas asynchronous transmission mode devices and processor devices byutilizing the semiconductor device of this invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view showing the first embodiment of thisinvention.

FIG. 2 is a cross sectional view showing the semiconductor device of theconventional art.

FIG. 3 is a graph showing the energy band diagram illustrating theelimination of the body floating effect in the semiconductor device ofthe conventional art.

FIG. 4 is a cross sectional view showing the semiconductor device of theconventional art.

FIG. 5 is a cross sectional view showing the semiconductor device of theconventional art.

FIGS. 6A and 6B are graphs showing the effect of the invention.

FIG. 7 is a cross sectional view showing the first embodiment of thisinvention.

FIG. 8 is a cross sectional view showing the second embodiment of thisinvention.

FIG. 9 is a cross sectional view showing the third embodiment of thisinvention.

FIG. 10 is a schematic diagram of the NAND circuit illustrating thethird embodiment of this invention.

FIG. 11 is a cross sectional view showing the fourth embodiment of thisinvention.

FIG. 12 is a cross sectional view showing the fifth embodiment of thisinvention.

FIG. 13 is a schematic diagram illustrating the fifth embodiment of thisinvention.

FIG. 14 is a structural view of the DRAM (dynamic memory) device forillustrating the fifth embodiment of this invention.

FIG. 15 is a cross sectional view showing the sixth embodiment of thisinvention.

FIG. 16 is a structural view of the SRAM device for illustrating thesixth embodiment of this invention.

FIG. 17 is a schematic diagram illustrating the sixth embodiment of thisinvention.

FIG. 18 is a structural view of the asynchronous transmission mode (ATM)system for illustrating the seventh embodiment of this invention.

FIG. 19 is a cross sectional view of the computer illustrating theeighth embodiment of this invention.

FIG. 20 is drawing showing the overall configuration of this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In this invention, holes emitted by the strong electric field of thedrain are accumulated in the single crystalline Si layer 3, recombinedwith electrons in the recombination center region and eliminated. Ionimplantation through the contact hole 19 which is connecting holes forthe source and drain electrodes 12 and 13 to form the recombinationcenter region 20 is the most effective method.

A material that will not form a barrier against the injection of holescurrent in the implanted region is selected as the fundamental elementfor ion implantation. Rare earth gas fundamental elements such as neon(Ne), argon (Ar), Group IV fundamental elements such as Si, Ge orhalogen fundamental elements such as chlorine (Cl) may be utilized.Boron (B) that will form a P-type conduction region may also beimplanted in the case of nMOS. However, when ions are implanted to formN conductive material such as phosphorus (P) and arsenic (As) then abarrier to the flow of holes is formed, the flow of holes in therecombination-center region 20 becomes difficult and the ability toeliminate the body floating effect is drastically weakened so thismaterial is not preferred.

In the ion implantation sequence, the ion implantation dosage is set sothat the single crystalline Si layer 3 will become amorphous and theimplantation energy set so that the amorphous region will reach theinsulator layer 2. The amorphous region (recombination-center region 209formed on the insulator layer 2 by means of ion implantation, maintainsa Polycrystalline condition without regrowing to the single-crystallinecondition in the subsequent manufacturing processes normally performedwith heat treatment at 1000 degrees centigrade and functions as asatisfactory recombination-center region. Ion species with an atomicweight of less than 10 are not preferred for use as ion species becauseof the difficulty in effectively forming an amorphous layer. Further,alkali metals such as Na, and K as well as rare earth metals containingmagnesium are not preferred since their diffusion coefficient inside thesingle-crystalline Si layer 3 is exceedingly large and might cause thereliability of the SOI-MOS device to deteriorate.

The injection angle for ion implantation when forming the source anddiffusion layer 9 and 10 in this invention is prone to cause thechanneling phenomenon to occur when perpendicular to the main surface ofthe SOI substrate 1 so a perpendicular injection angle is not preferred.In order to prevent the channeling phenomenon from occurring, aninjection angle tilted 10 to 30 degrees from the perpendicular positionrelative to the main surface of the SOI substrate 1 is preferred. Ionimplantation applied in this way will cause little spread in the lowconcentrated impurity region, form source and drain diffusion regions 9and 10 having a sharp distribution and leave a single crystalline Silayer 30 having a low concentration of P-type impurities of thespecified thickness below the source and drain layers 9 and 10.

Hereafter, this invention is described by utilizing the embodiments. Inorder to simplify the explanation, the drawings are shown with theessential portions enlarged. Factors such as the material, conductionand manufacturing conditions are not limited to the examples listed inthese embodiments and numerous adaptations are possible for eachembodiment.

First Embodiment

A cross sectional view for describing the first embodiment of thisinvention is shown in FIG. 7.

An SOI substrate is formed of a silicon oxide insulator (hereafterabbreviated to simply oxide insulator) 2 with a thickness of 300 nm anda single crystalline silicon layer 3 having a p-type impurityconcentration of 1×10¹⁶/cm³, crystal surface orientation (100) laminatedonto the handle wafer 1 constituting the single crystalline Si waferwith a diameter of 20 centimeters. A device isolation layer 4, a 5 nmthick gate insulator 5 and a gate electrode 6 made from an N-typelow-resistance Polycrystalline Si layer as well as a gate electrodeprotection insulator 7 are formed on the single crystalline siliconlayer 3 utilizing a manufacturing method of the known art for a MOSfield effect transistor. To form the gate insulator 5, ion implantationis selectively performed on the region planned for forming the gateelectrode of the single crystalline silicon layer 3. This ionimplantation may be performed after the gate insulator 5 is formed. Thegate length was formed at a length of 200 nm.

Implantation of arsenic (As) ions was performed under conditions of adosage of 3×10¹⁵/cm² and an acceleration voltage of 25 keV for use ofthe gate electrode protective insulator 7 and the gate electrode 6 as animplantation screen mask. Heat treatment for single crystallization wasperformed and a source diffusion region 9 of highly concentrated N-typeimpurities and a drain diffusion region 10 of highly concentrated N-typeimpurities were formed. This ion implantation process was performedtwice at an ion injection (input) angle of ±20 degrees relative to aperpendicular to the handle wafer 1.

Upon measuring the depth profile concentration distribution of arsenicions implanted in a sample treated under the same conditions as thisembodiment, the channeling phenomenon was found to be greatly reduced, ajunction depth of 180 nm at a concentration of 1 10¹⁵/cm² and anextremely sharp impurity distribution was achieved. The p-type singlecrystalline silicon layer 3 remaining underneath the source and drainjunction therefore had a thickness of 180 nm in this embodiment. Theconcentration profile of impurities in this p-type single crystallinesilicon layer 3 can be set to the desired concentration profile byutilizing a method such as ion implantation.

After forming a silicon nitride layer with a thickness of 200 nm overthe entire surface by utilizing a CVD (chemical vapor deposition) methodof the known art, anistrophic dry etching was performed and only asilicon nitride layer selectively left on the side wall of the gateelectrode 6, the other portions are removed and a gate side-wallinsulator 8 thus formed.

An inter-metal insulator 11 is formed from a silicon oxide insulatordoped with P impurities and contact hole 19 (contact areas) then formedin the desired location by photo etching using the method of the knownart to form the structure shown in FIG. 7.

Next, Si ion implantation with a high ion dosage was performed in thesingle crystalline silicon layer 30 beneath the contact hole 19 and anamorphous recombination center region 20 formed. The implantation energyfor this ion implantation was set to obtain a maximum concentration atthe interface of the oxide insulator 2 and performed under conditions ofan acceleration energy of 130 keV and an implantation dosage of2×10¹⁵/cm². After this ion implantation, the highest temperature of theheat treatment performed up to the final manufacturing process was 750degrees centigrade for 10 minutes and the recombination center region 20obtained after the final manufacturing process was Polycrystalline.

This Si ion implantation and subsequent heat treatment was performed ona sample under conditions identical to the conditions for thisembodiment an upon conducting an optical measurement of therecombination characteristics, the recombination time was found to bewithin an exceedingly short 10⁻¹⁰ seconds and the Polycrystalline Siimplanted region was confirmed to play a role as therecombination-center region 20.

Following the above mentioned high dose ion implantation process, amethod of the known art such as sputtering was utilized to form ametallic wiring layer constituted mainly of thin TiN as well asaluminum. Patterning according to the desired circuit configuration wasperformed and wiring formed containing the source electrode 12 and thedrain electrode 13 to form the semiconductor device shown in FIG. 1.

In this manufacturing process, instead of utilizing ion implantation, aconsecutive contact hole can also be formed into the single crystallinesilicon layer 3 after forming of the contact hole 19 in the inter-metalinsulator 11 and when then forming the metallic wiring layer, the singlecrystalline silicon layer 3 formed with the contact hole can be refilledby the metallic wiring layers 12 and 13 in a structure with the sourcediffusion region 9 and the single crystalline silicon layer 3simultaneously shorted. A recombination center region 20 can thus beformed as specified by means of the metal-semiconductor junction betweenthe metallic wiring layers 12 and 13 and the single crystalline siliconlayer 3. In this case, the recombination center region 20 withboundaries specified by the metal-semiconductor junction, ispositionally aligned with the source electrode 12 and the drainelectrode 13. Even if the recombination center region 20 is formed bymeans of metal-semiconductor junctions in this manner, thecharacteristics will be absolutely identical to the case when therecombination center region 20 was formed by ion implantation and thisstructure was confirmed to be remarkably effective in eliminating thebody floating effect.

The source—drain breakdown voltage of the semiconductor device of thisembodiment was 5.7 volts, an improvement of 2.5 volts compared to anSOI-MOS device of the conventional art fabricated to the same dimensionsand not having a recombination center region 20 formed by Si ionimplantation. The semiconductor device of this embodiment alsomaintained the same breakdown voltage characteristics as a MOS of thesame dimensions manufactured on the usual semiconductor substrate.Further, in terms of electrical current and voltage characteristics, theabnormal hump characteristic referred to as the kink characteristics wasnot observed and normal characteristics were shown. Further, as afunction of gate voltage, the dependence of source—drain currentresulting in leakage current observed as a low gate voltage in SOI-MOSdevices of the conventional art was not found in the SOI-MOS device ofthis embodiment. Also the characteristic observed in SOI-MOS devices ofthe conventional art in which fluctuations occurred due to thedependence of the threshold voltage on the drain voltage was notobserved in this embodiment. The fact that a leakage current at a lowgate voltage was not observed in this embodiment shows that therecombination center region (Si ion implantation region) 20 formed incontact with the bottom surface of the drain diffusion region 10 doesnot exert an adverse affect on the transistor characteristics.

These results clearly show that the semiconductor device of thisembodiment is completely free from the problems causing by the bodyfloating effect found in SOI-MOS devices of the conventional art. Theabove results allow concluding that holes emitted by the strong electricfield of the drain and injected into the P-type single crystallinesilicon layer 3 beneath the source diffusion region 9, are ejected intothe recombination center region 20 and completely eliminated. Also, thefact that no leakage current was observed is due to the P-type singlecrystalline silicon layer 3 beneath the drain diffusion region 10 beingdepleted upon application of a drain voltage so that the current flowpath for to the recombination center region 20 beneath the draindiffusion region 10 is cut off and therefore no abnormalities occurs inthe current-voltage characteristics.

The source and drain were replaced in each of the above measurements yetno differences were found which demonstrates that drain and source aresymmetrical in the semiconductor device of this invention. These resultsfurther demonstrate that the semiconductor device of this invention canbe applied to bidirectional transistors (transfer MOS) in which the roleof the source and drain are replaced by means of the operational timing.

Second Embodiment

The second embodiment of this invention is described while referring toFIG. 8. First of all, just as with the first embodiment, after formingthe gate electrode 6, arsenic (As) ions are implanted into the singlecrystalline layer 3 with the gate 6 as an ion implantation screen mask,subsequent activizing heat treatment performed, and an extremely shallowN-type source diffusion region 91 with a junction depth of 30 nm and anN-type drain diffusion region 10 are formed. The ion implantation wasperformed at an acceleration energy of 10 keV, and an ion implantationdosage of 2×10¹⁴/cm². The ion input (incident) angle was 20 degreesrelative to a position perpendicular to the substrate surface.

Next, after forming the gate side-wall insulator 8 in the same manner asthe first embodiment, a source diffusion region 9 and a drain diffusionregion 10 were formed by ion implantation with deeper depth and a higherconcentration than the above mentioned N-type source diffusion region 91and N-type drain diffusion region 101. After further forming theinter-metal insulator 11, the contact hole 19 was formed at the desiredlocation according to the first embodiment.

The recombination center region 20 was selectively formed with the samemethod as the first embodiment to contact the bottom surfaces of thesource and drain diffusion regions 9 and 10 as well as the upper surfaceof the insulator (oxide layer) 2 within the single crystalline siliconlayer 3 beneath the contact hole 19. However, in this embodiment therecombination center region 20 was formed by implantation of BF₂ ionsinstead of silicon (Si).

Processing just as in the first embodiment was performed and the wiringformed containing the source electrode 12 and the drain electrode 13 andthe semiconductor device thus manufactured as shown in FIG. 8.

The semiconductor device formed in this embodiment showed the samecharacteristics as the semiconductor device of the first embodiment andthough confirmed as effective in eliminating the SOI-MOS body floatingeffect, the current embodiment had a source—drain breakdown voltage anadditional 2 volts higher than the semiconductor device of the firstembodiment and furthermore had no gate induced drain leakage phenomenonin which a source-drain leakage current tends to increase when theapplied negative gate voltage is increased. This absence of gate induceddrain leakage is due to a weakening of the electric field of the draindue to the shallow drain diffusion region 101. The strong electric fieldof the drain just beneath the gate which occurs due to application of anegative gate voltage consequently weakened so no gate induced drainleakage was observed.

In this embodiment also, the recombination center region 20 may beformed by means of the metallic wiring layer 19 as shown in FIG. 20.

Third Embodiment

A cross sectional view of the third embodiment of this invention isshown in FIG. 9. FIG. 10 is a NAND gate logic circuit formed utilizing aportion of the semiconductor device shown in FIG. 9. In FIG. 10 theplurality of transistors enclosed by the broken line “a” are alltransistors having the same structure as shown in FIG. 9.

As shown in FIG. 9, in this embodiment, gate electrodes 6, 61, and 62are formed at specified sections of the P-type single crystallinesilicon layer 3 separated by a device isolation layer 4 and an insulator2. The source diffusion region 9 and the drain diffusion region 10 arerespectively connected to the source electrode 12 and the drainelectrode 13. Also, prior to forming the gate electrodes 6, 61, 62 ontothe single crystalline silicon layer 3 below the bottom surface of theN-type highly concentrated diffusion regions 91 and 92, B ionimplantation is performed beforehand and a P-type impurity region 31 isformed at a relatively high impurity concentration to a maximum of1×10¹⁸/cm3. Portions other than mentioned above are processed in thesame manner as the first embodiment.

As shown in FIG. 10, three P-channel MOS transistors T₁, T₂, T₃ areformed separately on a portion of the SOI substrate, in themanufacturing process differing from that of the first embodiment. Thegate electrodes for these three P-channel MOS transistors T₁, T₂, T₃ arerespectively connected to the above mentioned MOS gates 6, 61, and 62shown in FIG. 9. These mutually connected gate electrodes arerespectively the inputs IN1, IN2, and IN3 of the respective NAND gates.

In FIG. 10, the symbol OUT, is the NAND gate output, Vcc is power supplyline voltage and Vss is the earth voltage.

In the semiconductor device of this embodiment, the positive carriersemitted at the edge of the drain diffusion region 10 arrive and areejected into the recombination center region 20 at the bottom of thesource diffusion region 9 by way of the highly-concentrated impurityregion 31 regardless of the input, in whatever order a voltage isapplied to the inputs IN1, IN2 and IN3. This phenomenon is not dependenton the voltage potential of the diffusion regions 91 and 92.Accordingly, in the semiconductor device of this embodiment, just aswith the first embodiment, no evidence of the body floating effect wasobserved and the characteristics of the semiconductor device of thisembodiment were confirmed as satisfactory.

Fourth Embodiment

A cross sectional view of the semiconductor device of the fourthembodiment of this invention is shown in FIG. 11. The source and draindiffusion regions 9 and 10 with a high concentration of impurities aswell as a gate side-wall insulator 8 were formed with processingidentical to that of the first embodiment. Next, heat treatment wasperformed after forming a cobalt (Co) layer over the entire surface, andsiliciding of the cobalt (Co) layer on the exposed portion of the sourceand drain diffusion regions 9 and 10 performed to selectively form acobalt silicide layer 21 with a thickness of 50 nm, and selectivelyremove a non-reactive cobalt (Co) layer formed on the gate electrodeprotective insulator 7 and the device isolation layer 4, etc. Silicidealloy of a refractory metals such as titanium silicide, tungstensilicide, molybdenum silicide or nickel silicide or even a refractorymetal layer itself may be used instead of the cobalt silicide layer 21.

The next processing was performed in the same manner as the firstembodiment but argon (Ar) was utilized as the ion species for ionimplantation by way of the connecting hole or contact area 19. Theacceleration energy was set at 150 keV for the implanted argon topenetrate the cobalt silicide layer 21 and reach the interface of thesingle crystalline silicon layer 30 and the insulator 2, and therecombination center region 20 formed. Other manufacturing conditionswere the same as the first embodiment. Also, after the argonimplantation, heat treatment at 700° C. was performed to lower theresistance of the cobalt silicide layer 21.

In this embodiment, despite the fact that the maximum heat treatmenttemperature after forming the recombination center region 20 was a lowtemperature of 700° C., the resistance of the cobalt silicide layer 21was sufficiently lowered. Furthermore, except for the regionion-implanted with the argon, the contact resistance between the cobaltsilicide layer 21 and high impurity source and drain diffusion regions9, 10 was sufficiently lowered and the series source resistance couldalso be lowered sufficiently. As a result, the recombination centerregion 20 was formed without exerting any adverse effects on thetransistor characteristics and the SOI-MOS floating body effect waseliminated just the same as in the first embodiment.

In this embodiment also, the recombination center region 20 may beformed by means of the metallic wiring layer 19 as shown in FIG. 20rather than ion implantation.

Fifth Embodiment

FIG. 12 is a cross sectional view showing the fifth embodiment of thisinvention. FIG. 13 is a schematic illustrating the semiconductor deviceof the fifth embodiment of this invention. FIG. 14 is a structural viewof the DRAM(dynamic memory) device of the fifth embodiment of thisinvention.

After forming the device isolation layer 4 and the gate insulator (gateoxide) 5 with the same processing as the first embodiment, a gateelectrode (word line) is formed consisting of a heavily P-dopedPolycrystalline Si layer 6 as well as a TiN/W double layer 61 as shownin FIG. 12 and a silicon nitride gate electrode protection insulator 62consisting of a silicon nitride layer is formed above thePolycrystalline Si layer 6. Next, after selectively forming a gateside-wall protective insulator 8 from a silicon nitride layer on theside wall of the above mentioned gate electrode by a method of the knownart, ion implantation of arsenic (As) into the single crystallinesilicon layer 3 is performed as an implantation screen mask such as forthe gate electrode, heat treatment activation performed and N-typehighly-concentrated diffusion regions 9, 10 and 93 formed as the sourceand drains.

Next, an intermetal insulator layer 11 consisting of an SiO2 filmutilizing a CVD (chemical vapor deposition) method of the conventionalart is formed over the entire surface and after further forming a secondlevel inter-level metal insulator 81 over the entire surface, thesurface is flattened by performing chemical mechanical Polishing with amethod of the known art.

Contact holes are formed by utilizing photo etching of the known art atspecified portions of the inter-metal insulators 11 and 81 and thesurface of the diffusion layer 10 connected to the bit line is exposed.Silicon ions are implanted through the contact hole formed in thatprocess and a recombination center region 20 contacting the uppersurface of the insulator (oxide layer) 2 and the bottom surface of thediffusion region is formed in the single crystalline silicon layer 3.Any ion species may be used as the ion implantation provided thatimplanted region does not form barrier to the flow of holes. Instead Ar(argon) as an implantation species, a Group IV fundamental elements suchas Ge, rare earth gases such as neon (Ne), or halogen gases such aschlorine (Cl) may be used. An boron (B) implantation additive forming aP-type conductive may also be used. However, when ion implantation thatforms N-type conductive such as phosphorus (P) or arsenic (As) isperformed, barriers to hole flow are formed and the capability toeliminate body-floating effect drops drastically so this type of ionimplantation is not preferred.

An amorphous silicon layer 23 heavily doped with phosphorus is formedover the entire surface and after filling the contact holes, the siliconlayer 23 in portions other than in the contact holes is removed by achemical-mechanical Polishing process of the known art. A laminatedlayer consisting of an amorphous silicon layer 23 and a tungstensilicide layer 25 is formed, patterning performed according to thedesired circuit configuration and bit lines formed.

After forming the laminated layers of the silicon oxide layer 26 and thesilicon nitride layer 27, a (through) hole is formed by photo etchingwith a method of the known art to penetrate through the silicon nitridelayer 27, the silicon oxide layer 26, the second-level metal insulator81 and the inter-metal insulator 11. The surfaces of the N-type highlyconcentrated impurity diffusion regions 9, 93 are then exposed tofunction as capacitor element connection nodes. Further, the P-dopedamorphous silicon layer 28 is formed over the entire surface and filledinto the above mentioned contact holes.

In FIG. 12, the amorphous silicon layer 28 filled inside the contactholes appears to intersect the bit lines 24 and 25 however the crosssection of the capacitor element connection nodes is listed on thedrawing at the same cross section as the bit line connecting holes andactually have mutually different cross sections which do not contacteach other.

After filling the capacitor element connection node connection holeswith the P-doped amorphous silicon layer 28, an SiO₂ layer (not shown inthe drawing) with a thickness of approximately 2 μm is formed over theentire surface of the amorphous silicon layer 28. A tubular protrudingpattern is then formed by photo etching using a method of the known art.The P-doped amorphous silicon layer is left only on the side walls ofthis protruding pattern by using a method of the known art foranistrophic etching on a P-doped amorphous silicon layer and anelectrode 28 for one of the capacitor element formed.

After removing the above mentioned tubular protruding pattern, a thininsulator layer (not shown in the drawing) made from a silicon nitridelayer and a matching electrode referred to as plate electrode 29 madefrom a TiN are formed on the surface of the above mentioned one exposedelectrode 28 by utilizing a method of the known art.

The semiconductor device of this embodiment having the memory unitsshown in FIG. 13 is comprised with a DRAM (dynamic memory) device as themain component. In other words, a memory cell is formed by seriallyconnecting one semiconductor device Q_(T) of this invention with onecapacitor C_(s), and the memory cell then connected to a bit line fordata transmission and a word line for input/output control.

The DRAM (dynamic memory) device is comprised of memory cells made up ofmemory cell arrays arranged in a matrix and peripheral control circuits.The peripheral control circuits also, are comprised of the semiconductordevice of the first embodiment. In order to reduce the number of memorycell select address signal terminals, the string address signals and rowaddress signals are shifted and multiplexed. The RAS and CAS are thepulse signals. These RAS and CAS pulse signals control the clockgenerators 1 and 2 and distribute the address signals to the row decoderand string decoder. The designated word line and bit lines are selectedaccording to the address signal allocated from the row decoder andstring decoder by means of an address buffer (circuit). A sensingamplifier is connected by means of a flipflop type amplifier to each bitline to amplify the signals read out from the memory cells. A pulsesignal WE controls the switching between writing and read out bycontrolling a write clock generator. The pulse signal D is a write andread signal.

The semiconductor device of this embodiment eliminates the body floatingeffect, not just in the peripheral control circuits but in the memorycell array as well. The memory cell refresh characteristic whichdetermines the DRAM power consumption has been improved approximately 10times over the conventional art in a 16 megabit memory configuration andis 0.8 seconds even in the worst case. This high speed operation wasachieved by reducing the parasitic capacitance by means of the SOIstructure. The improvement in the refresh characteristic may beattributed to reducing the junction surface area in the SOI structureand removing fluctuations in threshold voltage by eliminating the bodyfloating effect however, since the recombination center region 20 usedto eliminate the body floating effect is only formed beneath the bitline diffusion layer 10 and is not formed beneath the highlyconcentrated impurity diffusion regions 9 and 93 of the capacitorelement connection nodes, the junction characteristics of the diffusionregions 9 and 93 for the capacitor element connection nodes are notaffected and no increase in leakage current occurred.

Sixth Embodiment

FIG. 15 is a cross sectional view showing the sixth embodiment of thisinvention. FIG. 16 is a structural view of the SRAM (statistically readout and write memory) device for illustrating the sixth embodiment ofthis invention. A schematic illustrating the sixth embodiment of thisinvention is shown in FIG. 17.

In the fourth embodiment, after forming a device isolation layer 4 andseparating the active region of the P-type single crystalline siliconlayer 3, the phosphorus ion implantation processing and activating heattreatment is performed according to the desired circuit configurationfor changing the conduction direction of the activized region in thesilicon layer 3 and controlling the threshold voltage value, and thelow-concentrated N-type single crystalline layer 32 is formed.

Just the same as for the fourth embodiment, a gate electrode 6consisting of a gate insulator layer 5 and W layer and also a gateelectrode protection insulator 7 are formed in sequence on thelow-concentrated P-type single crystalline silicon layer 3 (portion notP-doped) and the low-concentrated N-type single crystalline layer 32.

A gate electrode 6 is utilized as the mask the same as in the fourthembodiment and As (arsenic) implanted into the low-concentrated P-typesingle crystalline silicon layer 3 side and BF₂ ions implanted into thelow-concentrated N-type single crystalline layer 32 side at animplantation angle of 20 degrees relative to the surface. Activationheat treatment was then performed and the N-type source diffusion region9, the N-type drain diffusion region 10, the P-type source diffusionregion 101 as well as the P-type drain diffusion region 90 were formed.The acceleration energy for each type of ion implantation was set toattain a final thickness of 10 nm for the single crystalline siliconlayer 3 between the upper surface of the insulator layer 2 and thebottom surfaces of the source and drain diffusion regions 9, 10, 90 and101.

Next, a gate side-wall insulator 8 with a thickness of 100 nm, a cobaltsilicide layer 21, an inter-metal insulator 11 and a recombinationcenter region 20 were formed with the same processing as for the fourthembodiment. Metallic wiring containing a ground potential electrode 12,an output node electrode 22 as well as a power supply electrode 13 wereformed as shown in the structure of FIG. 15.

In the semiconductor device (CMOS) of this embodiment, formed asdescribed above, no problems that might serve as factors in the bodyfloating effect were observed in either the pMOS or nMOS configurationsand no penetrating current which is evidence of the SOI-CMOScharacteristic body floating effect was observed to occur due tonegative fluctuations in the threshold voltages of the NMOS or positivefluctuations in the pMOS threshold voltage, between the ground potentialelectrode 12 and the power supply electrode 13.

The fact that no body floating effect was observed in the pMOS device isaccounted for by the electrons (minority carriers) generated in thechannel of the single crystalline layer 32, being injected into andeliminated in the recombination center region 20 formed beneath theP-type source diffusion region 10. In the semiconductor device of thisembodiment, the body floating effect in the pMOS and nMOS devices can beeliminated with one ion implantation and a high performance CMOS devicecan be achieved at a low production cost without a complex manufacturingprocess.

The SRAM device shown in FIG. 16 was formed by utilizing thesemiconductor device of this embodiment shown in FIG. 15. In this SRAM,a memory cell constituting one memory unit, is formed with two CMOSpairs of this embodiment and two MOS (transfer MOS) devices to controlsignal input and output. This SRAM is formed of peripheral controlcircuits and memory cell arrays having memory cells arranged in a matrixhowever, the peripheral circuits were also formed by utilizing thesemiconductor device of this embodiment.

The SRAM of this embodiment shown in FIG. 16 is basically the same asthe fifth embodiment shown in FIG. 14 however an address translationdetector was installed to attain a high speed, low power consumptionSRAM and the internal circuitry controlled by pulses emitted from thisdetector. Further, to attain high speed in the circuit from the addressbuffer to the decoder, a row decoder was formed in two stages from apredecoder and a main decoder. The chip select is a circuit designed toavoid data conflicts during reading and writing of information by way ofthe CS and WE signals and also to allow high speed operation.

Since this SRAM made use of an SOI-CMOS device of this embodiment thateliminated the body floating effect, the power supply voltage wasreduced from 3.5 volts to 2.0 volts, the access time was reduced morethan 35 percent compared to the prior art and high speed operation wasachieved. These effects were obtained by the reduced stray capacitancein the SOI-CMOS structure. Further, threshold voltage fluctuations wereremoved by eliminating the body floating effect and the operating rangeof the sensing amplifier was reduced and high speed operation achieved.

Seventh Embodiment

FIG. 18 is a structural view of the asynchronous transmission mode (ATM)system illustrating the seventh embodiment of this invention. This is asignal transmission processing unit involving an asynchronoustransmission method (called ATM switching) and made by utilizing thesemiconductor device of this embodiment.

In FIG. 18, the information signal serially transmitted at high speed byway of optical fibers is sent by way of a device that converts theoptical information to an electrical signal (O/E conversion) and toparallel data (S/P conversion) and input to an integrated circuit(BFMLSI) configured utilizing the semiconductor device of this inventionas shown in claims 1 through claim 8.

The electrical signal address-processed by this integrated circuit isoutput by an optical fiber after electrical/optical (E/O) conversion andparallel/serial conversion (P/S) are performed. The above mentionedBFMLSI integrated circuit is comprised of a multiplexer (MUX), buffermemory (BFM) and a demultiplexer (DMUX). The BFMLSI is controlled by amemory control LSI, and an LSI having a function to allot null addresses(null address FIFO memory LSI).

The signal transmission processing unit of this embodiment has aswitching function to send a high speed transmit signal independent onthe address for transmission, to the desired address at high speed. TheBFMLSI has an operating speed that is drastically slower than thetransmission speed of the optical signal being input so the BFMLSIcannot directly switch the signal that is input. The input signal istherefore temporarily stored and after switching the stored signal, amethod to convert the input to a high speed optical signal and send itto the desired address is utilized. The slower the operating speed ofthe BFMLSI, the greater the memory capacity that is required. However,in the ATM switcher of this embodiment, the BFMLSI is made by utilizingthe semiconductor device of this invention. Therefore, compared to theconventional art, the BFMLSI of this embodiment has an operating speedthat is three times faster, the necessary memory capacity of the BFMLSIhas been reduced to approximately one-third compared to the conventionalart and a great reduction in the price of the ATM switcher can beachieved.

Eighth Embodiment

FIG. 19 is a structural view of the computer illustrating the eighthembodiment of this invention. This working example described in theeighth embodiment of this invention is adapted for large, high speedcomputers connected with a plurality of processors 500 in parallel forprocessing commands and arithmetic operations.

The semiconductor device of this invention has a higher density andlower cost than the integrated circuit of the conventional art usingbipolar transistors so that components such as a processor 500, a systemcontrol unit 501 and a main memory unit 502 can be formed with sizeshaving dimensions from 10 to 30 mm. This processor 500, a system controlunit 501 as well as a data communication interface 503 made from acompound semiconductor device are mounted on the same ceramic substrate506. Also, the data communication interface 503 and a data communicationcontrol unit 504 are mounted on the same ceramic substrate 507.

The central processing unit (CPU) 508 of the computer is comprised ofthe ceramic substrates 506 and 507 and the ceramic substrate mountedwith the main memory unit 502. These ceramic substrates have a size ofapproximately 50 centimeters or less on one side. The internal datacommunication of this central processing unit (CPU) 508 and the datacommunication with a plurality of other central processing units (CPU)508 or the data communications between the data communication interface503 and input/output processor 505 packaged substrates are performed byway of the optical fiber 510 shown with the two-way arrow lines in FIG.19.

The semiconductor device of this invention utilized in the processor500, a system control unit 501 and the main memory unit 502 operate inparallel and at high speed, and data communications are performed usinglight as the medium so that the number of commands processed per secondcan be greatly increased.

This invention configured as described above, can eliminate the bodyfloating effect which is the most serious problem in semiconductordevices formed on SOI substrates. This invention, without increasing theoccupation area can also prevent generation of the kink characteristicin device current/voltage characteristics and the fluctuating thresholdvoltages that also cause the body floating effect. This invention alsoeliminates the body floating effect on p-MOS devices formed on SOIsubstrates and can also eliminate the body floating effect on CMOSdevices formed on SOI substrates. A semiconductor device havingextremely high speed and low power consumption as well as a variety ofsystems using such a semiconductor device can therefore be achieved.

A further effect is that the semiconductor device of this invention canbe made merely by a combination of semiconductor production technologyof the conventional art so there is no need to develop new productiontechnology. Accordingly, a high performance SOI-MOS device in which thebody floating effect is eliminated and having no latchups ormisoperation caused by alpha rays irradiation, can be easily produced ata low cost.

What is claimed is:
 1. A semiconductor device comprising: an insulatorlayer formed on a wafer, a single crystalline semiconductor layer formedon said insulator layer, and a MOS field effect transistor formed onsaid single crystalline semiconductor layer, wherein said singlecrystalline semiconductor layer comprises a first conductivity typeregion and a second conductivity type region being opposite conductivitytype to said first conductivity type region, wherein said firstconductivity type region functions as a source region and a drain regionof said MOS field effect transistor, wherein a lower surface of saidfirst conductivity type region is formed apart from said insulatorlayer, wherein a contact hole is formed to penetrate through said firstconductivity type region and filled with a metallic layer, wherein arecombination center region is formed of a metal-semiconductor junctionbetween said metallic layer and said single crystalline semiconductorlayer, and wherein an edge of said recombination center region ispositioned apart from an edge of said first conductivity type region,wherein said recombination center region is a non-single crystallineregion.
 2. A semiconductor device according to claim 1, wherein a lowersurface of said recombination center region contacts an upper surface ofsaid insulator layer.
 3. A semiconductor device according to claim 1,wherein a portion of said single crystalline semiconductor layer betweensaid first conductivity type region and said insulator layer becomes adepletion layer when a voltage is applied to said first conductivitytype region.